The Accumulator
The Accumulator is used as a general register to accumulate the
results of a large number of instructions. It can hold an 8-bit (1-byte) value
and is the most versatile register the 8051 has due to the shear number of
instructions that make use of the accumulator. Accumulator performs arithmetic
and logic functions. Accumulator is also responsible for conditional branching
and provides a temporary place in a data transfer operations within the device.
More than half of the 8051’s 255 instructions manipulate or use the accumulator
in some way.
The "R" registers
The "R" registers are a set of eight registers that are
named R0, R1, up to and including R7.
These registers are used as auxiliary registers in many
operations.
The Accumulator alone would not be very useful if it were not for
these "R" registers. The "R" registers are also used to
temporarily store values.
The "B" Register
The "B" register is very similar to the Accumulator in
the sense that it may hold an 8-bit (1-byte) value.
The "B" register is only used by two 8051 instructions:
MUL AB and DIV AB. It enables quick and easier way of multiplying or dividing a
number by another number, and stores the other number in "B" and
makes use of these two instructions.
Aside from the MUL and DIV an instruction, the “B” register is
often used as yet another temporary storage register much like a ninth
"R" register.
The Data Pointer (DPTR)
The Data Pointer (DPTR) is the 8051’s only user-accessible 16-bit
(2-byte) register. DPTR is used to point to data. It is used by a number of
commands which allow the 8051 to access external memory. When the 8051 accesses
external memory it will access external memory at the address indicated by
DPTR.
While DPTR is most often
used to point to data in external memory, many programmers often take advantage
of the fact that it’s the only true 16-bit register available. It is often used
to store 2-byte values which have nothing to do with memory locations.
The Program Counter (PC)
The Program Counter (PC) is a 2-byte address which tells the 8051
where the next instruction to execute is found in memory. When the 8051 is
initialized PC always starts at 0000h and is incremented each time an
instruction is executed. It is important to note that PC isn’t always
incremented by one. Since some instructions require 2 or 3 bytes the PC will be
incremented by 2 or 3 in these cases. The Program Counter is special in that
there is no way to directly modify its value.
The Stack Pointer (SP)
The Stack Pointer, like all registers except DPTR and PC, may hold
an 8-bit (1-byte) value. The Stack Pointer is used to indicate where the next
value to be removed from the stack should be taken from.
When you push a value onto the stack, the 8051 first increments
the value of SP and then stores the value at the resulting memory location.
When you pop a value off the stack, the 8051 returns the value
from the memory location indicated by SP, and then decrements the value of SP.
When the 8051 is initialized SP will be initialized to 07h. If you
immediately push a value onto the stack, the value will be stored in Internal RAM address 08h. This makes sense taking into
account what was mentioned two paragraphs above: First the 8051 will increment
the value of SP (from 07h to 08h) and then will store the pushed value at that
memory address (08h).
SP
is modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL,
RET, and RETI.
PSW Program Status Word
PSW, the Program Status Word is at address D0h and is a
bit-addressable register. The status bits are listed in table 1.1.
Table.1.1 Program Status Word
Symbol
Bit
|
Address
|
Description
|
C (or CY)
|
PSW.7 D7h
|
Carry flag
|
AC
|
PSW.6 D6h
|
Auxiliary carry flag
|
F0
|
PSW.5 D5h
|
Flag 0
|
RS1
|
PSW.4 D4h
|
Register bank select 1
|
RS0
|
PSW.3 D3h
|
Register bank select 0
|
0V
|
PSW.2 D2h
|
Overflow flag
|
PSW.1 D1h
|
Reserved
|
|
P
|
PSW.0 D0h
|
Even Parity flag
|
Carry flag(C)
This is a conventional carry, or borrows, flag used in arithmetic
operations. The carry flag is also used as the ‘Boolean accumulator’ for
Boolean instruction operating at the bit level. This flag is sometimes
referenced as the CY flag.
Auxiliary carry flag
(AC)
This is a conventional auxiliary carry (half carry) for use in BCD
arithmetic.
Flag 0(F0)
This is a general-purpose flag for user programming.
Register bank select 0 and register bank select 1. RS0 and RS1
These bits define the active register bank (bank 0 is the default
register bank).
Overflow flag. OV
This is a conventional overflow bit for signed arithmetic to
determine if the result of a signed arithmetic operation is out of range.
Even Parity flag (P)
The parity flag is the accumulator parity flag, set to a value, 1
or 0, such that the number of ‘1’ bits in the accumulator plus the parity bit
add up to an even number.
SFR Registers for the Internal Timer
TCON, the Timer Control register is an SFR at address 88h, which
is bit-addressable. TCON is used to configure and monitor the 8051 timers.
TMOD, the Timer Mode register is an SFR at address 89h and is used to define
the operational modes for the timers. TL0 (Timer 0 Low) and TH0 (Timer 0 High)
are two SFR registers addressed at 8Ah and 8Bh respectively. The two registers
are associated with Timer 0.
TL1 (Timer 1 Low) and TH1 (Timer 1 High) are two SFR registers
addressed at 8Ch and 8Dh respectively. These two registers are associated with
Timer 1.
Power Control Register
PCON (Power Control) register is an SFR at address 87h. It
contains various control bits including a control bit, which allows the 8051 to
go to ‘sleep’ so as to save power when not in immediate use.
SerialPort Registers
The SCON (Serial Control) is an SFR register located at addresses
98h, and it is bit-addressable. SCON configures the behavior of the on-chip
serial port, setting up parameters such as the baud rate of the serial port,
activating send and/or receive data, and setting up some specific control
flags.
The SBUF (Serial Buffer) is an SFR register located at address
99h. SBUF is just a single byte deep buffer used for sending and receiving data
via the on-chip serial port.
Interrupt Registers
IE (Interrupt Enable) is an SFR register at addresses A8h and is
used to enable and disable specific interrupts. The MSB bit (bit 7) is used to
disable all interrupts.
IP (Interrupt Priority) is an SFR register at addresses B8h and it
is bit addressable. The IP register specifies the relative priority (high or
low priority) of each interrupt. On the 8051, an interrupt may either be of low
(0) priority or high (1) priority.
4.4.1 PIN DESCRIPTION
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s are written to port 0
pins, the pins can be used as high impedance inputs.
Port 0 may also be configured to be the multiplexed low order
address/data bus during accesses to external program and data memory.
In this mode P0 has
internal Pull-ups. Port 0 also receives the code bytes during Flash
programming, and outputs the code bytes during program verification. External
pull-ups are required during program verification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull ups.
The Port 1 output buffers can sink/source four TTL inputs. When 1s are written
to Port 1 pins they are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pull-ups.
Port 1 also receives the low-order address bytes during Flash
programming and verification.
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups.
The Port 2 output buffers can sink/source four TTL inputs. When 1s are written
to Port 2 pins they are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally being pulled low will source
Current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from
external program memory and during accesses to external data memory that uses
16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that uses
8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special
Function Register.
Port 2 also receives the high-order address bits and some control
signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups.
The Port 3 output buffers can sink/source four TTL inputs. When 1s are written
to Port 3 pins they are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally being pulled low will source
current (IIL) because of the pull-ups.
Port 3 also serves the functions of various special features
of the AT89C51 as listed below:
Port 3 Functions
Port 3 also receives some control signals for Flash programming
and verification.
RST
Reset input. A high on this pin for two machine cycles while the
oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the
address during accesses to external memory. This pin is also the program pulse
input (PROG) during Flash programming.
In normal operation ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and may be used for external timing or clocking purposes.
Note, however, that one ALE pulse is skipped during each access to external
Data Memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR
location 8EH. With the bit set, ALE is active only during a MOVX or MOVC
instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable
bit has no effect if the microcontroller is in external execution mode.
PSENProgram Store Enable is the read strobe to external program
Memory. When the AT89C51 is executing code from external program memory, PSEN
is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to
enable the device to fetch code from external program memory locations starting
at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will
be internally latched on reset. EA should be strapped to VCC for internal
program Executions. This pin also
receives the 12-volt programming enable voltage (VPP) during Flash programming,
for parts that require 12-volt VPP.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier is XTAL2 pin.
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier which can be configured for use as an on-chip oscillator,
as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used.
To drive the device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2. There are no
requirements on the duty cycle of the external clock signal, since the input to
the internal clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum voltage high and low time specifications must be observed.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all the on chip
peripherals remain active. The mode is invoked by software. The content of the
on-chip RAM and all the special functions registers remain unchanged during
this mode. The idle mode can be terminated by any enabled interrupt or by a
hardware reset. It should be noted that when idle is terminated by a hard ware
reset, the device normally resumes program execution, from where it left off,
up to two machine cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in this event, but access to
the port pins is not inhibited.
To eliminate the possibility of an unexpected write to a port pin
when Idle is terminated by reset, the instruction following the one that
invokes Idle should not be one that writes to a port pin or to external memory.
POWER
DOWN MODE
In the power-down mode, the oscillator is stopped, and the
instruction that invokes power-down is the last instruction executed. The
on-chip RAM and Special Function Registers retain their values until the
power-down mode is terminated. The only exit from power-down is a hardware
reset. Reset redefines the SFR’s but does not change the on-chip RAM. The reset
should not be activated before VCC
is restored to its
normal operating level and must be held active long enough to allow the oscillator
to restart and stabilize.
AT89C51 RESET
- RESET
is an active high input.
- When
RESET is set to high, AT89C51 goes to the power on state.
- Power-On
Reset.
- Push
PB and active high on RST.
- Release
PB, Capacitor discharges and RST goes low.
- RST must stay high for a min of 2 machine cycles.
The 8051 has two internal
sixteen bit hardware Timer/Counters. Each Timer/Counter can be configured in
various modes, typically based on 8-bit or 16-bit operation. The 8051 product
has an additional (third) Timer/Counter.
8-bit COUNTER OPERATION
First let us consider a simple 8-bit counter. Since this is a
modulo-8 set up we are concerned with 256 numbers in the range 0 to 255 (28
=256). The counter will count in a continuous sequence as follows:
Hex Binary Decimal
00h 00000000 0
01h 00000001 1
02h 00000010 2 . .
FEh 11111110 254
FFh 11111111 255
00h 00000000 0 here the counter overflows to zero1
01h 00000001 1
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